1. Field of the Invention
The present invention relates to an insulated-gate field-effect transistor having a suppressed short channel effect, particularly to a double-gate field-effect transistor, and to an integrated circuit employing the transistor and a method of manufacturing the transistor.
2. Description of the Prior Art
In order to achieve insulated-gate field-effect transistors with shorter channel lengths, it is necessary to suppress the short channel effect (the threshold voltage roll-off that occurs when the channel length is shortened). The double-gate field-effect transistor disclosed by Japanese Patent No. 2,021,931 has a device structure for achieving that. FIG. 1 is a cross-sectional view of a conventional double-gate field-effect transistor.
With reference to FIG. 1, the transistor includes a substrate 501, a lower gate insulation film 502, a source region 503, a drain region 504, a channel region 505, an upper gate insulation film 506, an insulation film 507, an upper gate electrode 508, a lower gate electrode 509, a source electrode 530, and a drain electrode 540. This structure is a highly effective method of suppressing the short channel effect. This is because the upper gate electrode 508 and the lower gate electrode 509 shield the channel region 505. By thereby suppressing the effect that the drain field has on the potential distribution at the interface region between the source and the channel, it is possible to stabilize just the channel potential, even if the channel is shortened, thereby suppressing the threshold voltage roll-off caused by the short channel effect.
However, to enable this feature of the structure to function effectively in a high-performance integrated circuit device, there must be no positional misalignment between the channel region and the two gate electrodes. Misalignment increases parasitic capacitance and resistance that, together with the fluctuations thereof, can lead to a marked degradation in device performance.
With the structure of the conventional double-gate field-effect transistor in which the vertically arranged gate electrodes, separated by the channel region, together with the source and drain regions, are not provided on the same principal surface, self-alignment cannot be employed, making it difficult to form the two gate electrodes in alignment with the channel, source and drain regions. It has therefore been necessary to utilize the available positioning accuracy with respect to the disposition of the lower gate electrode and channel region, and this has given rise to the problem of performance degradation arising from such factors as increased parasitic capacitance and fluctuations thereof. Another drawback is that when the fabrication is used as an integrated circuit device, because the upper and lower gate electrodes are not positioned on the same principal surface, the wiring becomes complex. To resolve such problems, the present invention proposes a double-gate field-effect transistor having the configuration shown in the plan view of FIG. 2 and the cross-sectional view of FIG. 3.
With further respect to the double-gate field-effect transistor of this configuration, normally chemical mechanical polishing (CMP) is used for surface planarization. CMP and other planarizing processes can easily cause contamination and damage, and are followed by washing that itself involves many process steps. It is therefore desirable to reduce the number of planarizing steps as much as possible. Thus, another object of the present invention is to reduce the number of steps used to planarize surfaces using CMP and the like.
To achieve the above object, the present invention provides a double-gate field-effect transistor comprising a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film and each made from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other, the two gate electrodes being formed in opposition on a principal surface of the insulation film on which the channel region is formed, with the channel region between the gate electrodes.
With reference to FIGS. 3 and 4, a semiconductor crystal layer 3 is prepared that is isolated from the substrate by an insulation film 2. A semiconductor crystal layer island comprising at least a source region and a drain region, and a channel region adjacent to the source and drain regions, is isolated from the surrounding portion by a trench. Gate insulation films 71 and 72 are formed on opposing side faces of the channel region exposed in the trench, and this is followed by the formation of gate electrodes 81 and 82. These steps produce a structure provided with a semiconductor-layer island, and gate electrodes provided in the trench, with the gate electrodes being mutually isolated from each other by the gate insulation film. The semiconductor island region 9 between the gate electrodes has a predetermined width that preferably is less than the length of the channel region. It is desirable to make this width small enough to enhance the short channel effect suppressive property of the semiconductor-layer island.
Thus, a first principal point of the present invention is that a double-gate field-effect transistor comprising a substrate, an insulation film 2 formed on the substrate and a source region 10, drain region 11 and channel region 9 constituted from a semiconductor crystal layer 3 formed on the insulation film 2 provided on a substrate, has two insulated gate electrodes electrically insulated from each other, the two gate electrodes facing each other on the same principal surface of the channel region, with the channel region therebetween.
A second principal point of the present invention is that the double-gate field-effect transistor that is the first principal point is used to realize a high-performance integrated circuit.
A third principal point of the present invention is that the above integrated circuit includes double-gate field-effect transistors having channel regions of different width.
Also, to enable the width of the channel region to be substantially doubled by applying the same input signal to the two insulated gate electrodes, a fourth principal point of the present invention is that the double-gate field-effect transistor is operated by electrically connecting the two insulated gate electrodes thereof.
By using an input of different signals to the two insulated gate electrodes that are connected in parallel with the gate voltage characteristics mutually balanced, to thereby enable the transistor to be used as two transistors, a fifth principal point of the present invention is that the double-gate field-effect transistor is operated by electrically connecting a different electric potential to the two insulated gate electrodes thereof.
Since the short channel effect can be suppressed by optimizing the electric potential at one of the two insulated gate electrodes, a sixth principal point of the present invention is to operate the double-gate field-effect transistor according to the fifth principal point by connecting a substantially fixed electric potential to one of the two insulated gate electrodes thereof.
A seventh point of the present invention relates to a method of manufacturing the double-gate field-effect transistor by steps that include a step of forming a trench in a semiconductor layer that is isolated from a substrate by a first insulation layer and is formed on a surface of a second material that forms an etching mask for a first material, with the trench being of a depth that extends to the surface of the first insulation layer and two side faces of a portion of the semiconductor layer having a predetermined width being exposed in the trench; a step of using the first material to bury and planarize the trench; and a step of using a transverse plane geometry pattern that cuts across a portion having the predetermined width to remove material from the trench other than the first material portion and leave an island of the first material.
In accordance with an eighth principal point of the present invention, the manufacturing method includes a step of forming on the side faces of the semiconductor layer exposed in the trench, a second insulation layer that forms an etching mask for the first material.
In accordance with a ninth principal point of the present invention, the manufacturing method includes a step of introducing impurity from a side face of the semiconductor layer portion, using the first material island portion as a mask.
In accordance with a tenth principal point of the present invention, the manufacturing method includes a step of using a third insulation material to planarize the trench except for the first material island portion.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and following detailed description of the invention.